| 摘要 |
PURPOSE:To make the reduction of junction capacitance and short channelling compatible by surrounding the side sections and bottoms of each P type and N type well by a semiconductor region of a conduction type reverse to a substrate or a well region. CONSTITUTION:A P type epitaxial layer 4 is grown on one main surface of the P<+> type Si substrate 1 through N<+> type buried layers 2, 3, and the N type well 5 is formed to the layer 4. The well 5 is separated sufficiently from the regions 4, 1 owing to regions 6, 2 because the well 5 is formed while being in contact with the layer 2 and an N<+> type region unified with the layer 2 is formed to the side section. A memory cell is formed in the layer 4, and the side section and bottom of its element region are surrounded by an N<+> type region 13 and the layer 3. Consequently, substrate bias voltage can be applied to the wells apart from other wells because each P type well and N type well is formed as severally independent well. Accordingly, junction capacitance can be reduced while short channelling can also be attained. |
