| 摘要 |
PURPOSE:To reduce the pattern area of an integrated circuit, by using an address control circuit in time division by an instruction control circuit and adopting only one address control circuit for an RAM, register and a programmable logic array. CONSTITUTION:The instruction control circuit 1 designates a specific address by using the address control circuit 10 as an RAM address. The data in the RAM2 of the designated address is held in an arithmetic operation circuit ALU4. The data is inputted to the address control circuit 10 again, and a data output is obtained at the circuit 1 this time by using the output of the circuit 10 as an address input of the programmable logic array PLA5. In obtaining the data output of the register group, the circuit 1 designates the address of the register group 3 in place of the RAM2 to store the data of the register group in the circuit ALU4. Thus, the address control circuit 10 is used in time division. |
