| 摘要 |
PURPOSE:To perform a normal test without erroneous operation by serially applying data to avoid the use of a common data bus and eliminating the operation of a testing logic circuit in a testing register while testing data row is transferring. CONSTITUTION:6 bit serial data row which designates the first testing conditions is fed through an input terminal 4 to a register 3 in a time series manner. Then, the prescribed input is applied to the input terminal group 7. After the series data row is stably stored in the register 3, a signal is applied to a control signal input terminal to operate a control circuit 5, and the parallel data row of the register 3 is fed to logic circuit group. The statuses of the testing logic circuits 2a-2g are determined in response to the first testing conditions, and corresponding outputs are obtained from output terminals 8. When the outputs are as desired, the test result of these testing conditions is judged as being preferable. Then, the second, third testing conditions are applied, similar test are repeated, and the fact that normal output can be obtained in the respective cases are confirmed. |
