| 摘要 |
PURPOSE:To accelerate the restart of decoding of an instruction following a branch instruction, by releasing the inhibition of decoding by the branch instruction when there is no store type instruction. CONSTITUTION:A decoding inhibition tag is inputted as it is to the next stage only when a signal 21 is logic ''1''. When, however, the logic of the signal 21 is ''0'', it is inhibited by AND gates 22, 23, and 24 and the decoding inhibition tag is deleted at the next stage. For example, when only a tag ST14(19) has logic ''1'' and the decoding inhibition tag DCI0(6) also is logic ''1'', logic ''1'' is inputted to a DCI1(7), but the execution of an IS(4) ends and the output signal 21 of an OR gate 20 goes to logic [0]. Then, the output of an OR gate 11 goes to logic [0], so an instruction and data are prefetched from a branch destination address unless the signal 12 has logic ''1'' even if the deciding inhibition is released and the DCI0(6) is logic ''1'' to indicate a store instruction. |
