An input interface circuit for a logic device.

摘要

In input interface circuit (11) for a logic device which has a first transistor (Q1) whose base is supplied with an input signal (VI) and whose emitter is grounded through first and second resistors (R1, R2) and a second transistor (Q2) whose base is supplied with the potential of the node of the first and second resistors (R1, R2) and whose collector sends forth a logic signal. This input interface circuit (11) is further provided with a third resistor (Q3) connected between the second resistor (R2) and ground and a third transistor (Q3) whose current path is connected in parallel to the third resistor (R3) and whose base is connected to the collector of the second transistor (Q2).