发明名称 Parity bit lock-on method and apparatus
摘要 Method and apparatus for locking onto the parity bit of a bit stream of equal length words, each of which words includes a parity bit, are disclosed. The bit stream is shifted through a data shift register which includes a plurality of word length sections. Parity of bits contained in the first section of the data shift register is checked every bit interval of the bit stream. Two parity bit shift registers are provided, the first of which is one word in the length and the second of which is of the same length as the data shift register. The output from the parity checking means is connected to serial inputs of said first and second parity bit shift registers through a logic gate controlled by the serial output from the first parity bit shift register. When the serial output from the first parity bit shift register is a "one" bit, the results of the parity check are entered into said first and second parity bit shift registers through said logic gate, and when the serial output therefrom is a "zero" bit, a "zero" bit is entered into said first and second parity bit shift registers. Means are provided for connecting parallel outputs of said second parity bit shift register to a decision logic circuit having a word clock pulse output which is synchronized with parity bits in the bit stream when the apparatus is locked onto parity bits in the stream.
申请公布号 US4412329(A) 申请公布日期 1983.10.25
申请号 US19810311782 申请日期 1981.10.15
申请人 SRI INTERNATIONAL 发明人 YARBOROUGH, JR., JOHN M.
分类号 H04L7/04;(IPC1-7):H04L7/02 主分类号 H04L7/04
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