| 发明名称 |
FET MEMORY CELL STRUCTURE AND PROCESS |
| 摘要 |
<p>FET Memory Cell Structure and Process A dense, vertical MOS FET memory cell has a high charge storage capacitance per unit area of substrate surface. The charge storage capacitor structure is formed within a well etched in the silicon semiconductor substrate by a combination of reactive ion etching and a self-limiting wet etch. FI 9-79-083</p> |
| 申请公布号 |
CA1155972(A) |
申请公布日期 |
1983.10.25 |
| 申请号 |
CA19810379798 |
申请日期 |
1981.06.15 |
| 申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
FATULA, JOSEPH J., JR.;GARBARINO, PAUL L. |
| 分类号 |
H01L29/74;H01L21/306;H01L21/3065;H01L21/822;H01L21/8242;H01L27/04;H01L27/10;H01L27/108;H01L29/749;H01L29/78;H01L29/94;(IPC1-7):H01L21/302;H01L27/08 |
主分类号 |
H01L29/74 |
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