| 摘要 |
PURPOSE:To offer a PLL which attains sure and quick locking, by providing a phase shifter phase-shifting an output signal by (pi/2)+npi (where; n is an integer) for output for the pre-stage of a phase comparator. CONSTITUTION:In Figure, 4 is a pi/2 phase shifter, 5 is a multiplier, 6 is a low pass filter and 7 is a multiplier. When ¦omegae¦ is sufficiently larger against the frequency band of a loop filter 3, VCO1 is frequency-converted and the ¦omegae¦ is decreased. When the ¦omegae¦ enters the locking range of the PLL, the synchronism is attained rapidly and omegae=0 is attained. In case of the asynchronous state, the circuit is operated as an AFC circuit so as to decrease the frequency error and when the frequency error is within the range of synchronism, the PLL is operated as a phase synchronism circuit. |
