| 摘要 |
PURPOSE:To generate a stable clock signal, by applying an output of a time window generator to a pulse generator which shapes the pulse width of the input data signal inputted to a phase comparator and preventing the disturbance of a phase locked loop output due to an input failure data signal generated at the outside of the time window region at the end of synchronism. CONSTITUTION:The time window generator 6 sets a time window signal S12 at the end of asynchronism with a time window switching signal S13 and generates a pulse S2 applying an input data signal S1 from a pulse generator 7 to a phase comparator 2 unconditionally, generates the S12 at the end of synchronism by switching the S13, and when a leading (a) of the input data signal S1 is at the outside of the region of a time window (g), a pulse generator 7 limits the generation of pulses, allowing to prevent phase difference signals S3, S4 of the phase comparator 2 from being generated. |
