发明名称 INFORMATION PROCESSOR
摘要 <p>PURPOSE:To reduce the time required for synchronization in which the same instruction is executed plural times for synchronization of two programs, by adding a synchronizing circuit. CONSTITUTION:When the synchronization is required between microprograms FW1 and FW2, the program FW1 sets a synchronizing signal K at ''1''. At the same time, a selecting circuit SEL selects a decoding cycle signal B and an executing cycle signal C. On the other hand, a decoding cyclic flip-flop 1' is reset together with an executing cycle flip-flop 2' and a waiting cycle flip-flop FF3' respectively. Therefore a microinstruction is executed by signals B and C for the program FW2. Thus the synchronization is secured between programs FW1 and FW2. In case the FW2 is under a waiting cycle, the FF3' is reset by the signal K. As a result, the waiting state is released for the FF3' and therefore the FF3' is put under control of the FW1.</p>
申请公布号 JPS58182757(A) 申请公布日期 1983.10.25
申请号 JP19820065675 申请日期 1982.04.20
申请人 NIPPON DENKI KK 发明人 MIZUNO MASAKI
分类号 G06F9/26;G06F9/22;G06F9/28;G06F15/16;G06F15/177 主分类号 G06F9/26
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