PIPELINED DIGITAL PROCESSOR ARRANGED FOR CONDITIONAL OPERATION

摘要

BO?DIE-2 PIPELINED DIGITAL PROCESSOR ARRANGED FOR CONDITIONAL OPERATION A digital processor arranged for pipelined operation includes a common data and control bus and a source of instructions and data words. An arithmetic section processes one data word with another data word through selected processing subsections performing operations according to an expression, thereby producing a resultant data word. A destination receives the resultant data word from the arithmetic section. Control circuits (IR-C) decode a single conditional instruction for controlling performance of a specific condition test during a first subsequent processor cycle (i.e., i+2). The control circuits further decoding another instruction word during the first subsequent processor cycle for controlling all processing sections operations during a second subsequent processor cycle (i.e., i+3). A comparison circuit compares conditions existing in the digital processor during the first subsequent processor cycle with the specific condition information included in the conditional instruction and logic circuitry selectively disables control of at least one section of the digital processor during the second subsequent processor cycle.