| 摘要 |
PURPOSE:To change freely the period of the frequency division output without changing the period of a synchronizing signal and simplify the circuit constitution, by selecting the output of the first frequency dividing circuit by a selecting circuit and using this output as the input of the second frequency dividing circuit. CONSTITUTION:When a synchronizing signal phi is supplied, 4 binary counters 1-4 in the first frequency dividing circuit 5 divide the frequency of this signal successively by 2 synchronously with one another, and frequency division outputs Q1-Q4 of binary counters 1-4 become signals having 2-fold, 4-fold, 8-hold, and 16-fold periods of the synchronizing signal phi respectively, and one of instruction signals A-D is selected by a selecting circuit 6, and one of frequency division outputs Q1-Q4 of the first frequency dividing circuit is applied as an input Q0 to the second frequency dividing circuit and has the frequency divided by the period of the synchronizing signal phi, and frequency division outputs QA- QC are outputted. Since the change of instruction signals A-D suffices to change periods of frequency division outputs QA-QC, periods of frequency division outputs are changed relatively freely. |
