发明名称 BIT ALIGNMENT CIRCUIT OF 2-DIMENSIONAL MEMORY SYSTEM
摘要 PURPOSE:To decrease the hard quantity of a memory peripheral circuit for a 2- dimensional memory which is used in a nipple mode, by having the common alignment of bits between the horizontal and vertical image secondary array data. CONSTITUTION:A bit alignment circuit consists of a 4-1 selection circuit 18, a 0-3 bit left circular shift circuit 19, a shift register 20 and a 0-3 bit left circular shift circuit 21. The bit alignment circuit can pass through a processing path equal to a vertical reading data by converting artificially a horizontal reading data into a series type data equal to the vertical reading data.
申请公布号 JPS58169666(A) 申请公布日期 1983.10.06
申请号 JP19820052877 申请日期 1982.03.31
申请人 FUJITSU KK 发明人 MURATA TAKESHI
分类号 G06T1/60;G06F5/01 主分类号 G06T1/60
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