| 摘要 |
PURPOSE:To hold high reliability and to decrease hardware, by making the second control storage and the main storage have the same large capacity, providing an ECC circuit, and omitting the ECC circuit from the second control storage. CONSTITUTION:At the time of a regular operation, in case when a data is written in the first control storage 12-1, the same data is written in the same address in the second control storage 12-2, too. Also, to the data of the storage 12- 2, an ECC code is added from an ECC circuit 15. Also, when a processor 11 reads and writes to a memory device 6, read from the storage 12-1 is executed simultaneously. Moreover, in case when a parity error is detected in a read-out data from the storage 12-1, interruption is applied to the processor 11. The processor 11 checks the interruption cause, and when it is recognized that a parity error is generated in a read-out data from the storage 12-1, the processor reads out the data concerned from the storage 12-2, and corrects an error of the storage 12-1. In this case, the read-out address of the storage 12-2 is same as the error generating address. |
