| 摘要 |
PURPOSE:To reduce the area of a P-N-P-N type memory cell and to improve the switching speed of the cell in a semiconductor memory having the cells by employing as a wiring layer a buried layer and forming vertically all transistors forming the P-N-P-N type elements. CONSTITUTION:Transistors Q1, Q2, Q3 forming a P-N-P-N type half cell are all formed in a vertical type in a structure having an N-P-N type transistor QD for driving a word line. a P type buried layer 22 forming a wiring layer of a word line W<+>1, memory cells MC-1, 1 formed on the layer 22 and a P-N-P type transistor QS formed at the periphery of the memory cell formed on an N type semiconductor substrate 21, thereby accelerating the switching and reducing the irregular characteristics. Since the layer 22 is used as the wiring layer of the word line W<+>1, the metal wirings are reduced that much, two contacting windows per memory cell can be eliminated, the yield can be improved, and the area of the cell can be readily reduced. |
