| 摘要 |
<p>PURPOSE:To implement various timing signals with hardware which is minimized in volume, by making an arrangement that basic timing signals and asynchronous timing signals are implemented by various selecting circuits installed in a delay line circuit and the controlling circuit of the selecting circuits. CONSTITUTION:Delay lines 20-23, to which a tap interval selecting circuit is added respectively, a delay line 24, to which a repeating cycle selecting circuit is added, a circuit 25 for selecting the number of times of loop, and a delay line 30, to which a pulse width selecting circuit is added, are installed in a delay loop circuit 34. Furthermore, a pulse width controlling section 26, a tap interval controlling section 27, a section 28 for controlling the number of times of loop, and a cycle controlling section 29 are installed to the outside of the delay loop circuit 34 and the selecting circuits mentioned above are controlled. In this way, various signals are implemented with single hardware and the volume of the hardware is reduced.</p> |
