| 摘要 |
PURPOSE:To select sampling frequency and the number of quantitizing bits, by constituting so that the sampling frequency of an A/D converter and the number of quantitizing bits can be set optionally in accordance with the purpose respectively, by swtiching the clock frequency. CONSTITUTION:In case when a switch 29 is connected to T1, a master clock from a master clock generating part 27 is inputted to a various clock generating part 30. In this case, a clock signal outputted to each part, from the various clock generating part 30 is constituted so as to attain 50.4kHz as sampling frequency and 307.2kHz as data frequency of a recording signal. Subsequently, when the switch 29 is connected to T2, the master clock inputted to the various clock generating part 30 attains a signal whose frequency is divided into two. As a result, various clock signals outputted from the various clock generating part 30 all attain signals whose frequency is divided into two. |
