| 摘要 |
PURPOSE:To contrive improvement in the uniformity of the delay time between signals, in simplification of wiring and in efficiency of wiring work by a method wherein a suitable number of fundamental wirings are formed in the titled integrated circuit beforehand. CONSTITUTION:A contact X1 and/or X4 and Y1 and/or Y4 which are connected to the gate of a gate array, for example, formed in an element region 1a are provided, the contact X1 and/or X4 is connected to a clock phi1, and the other contact Y1 and/or Y4 is connected to a clock phi2. In this case, a pair of fundamental wiring 3a for clock (clock phi1) and 3b (clock phi2) extending in the longitudinal direction (array direction) are provided in a wiring region 1b. These fundamental wirings 3a and 3b for clock, which are extended making an almost straight line, have the length same as that of the wiring region, and are provided in the well-kown arrangement relations which will be used as the prestage for a mutual wiring design. |
