Clock recovery circuit with a phase-locked loop to recover a clock pulse string from an input pulse string

摘要

The clock recovery circuit has a phase-locked loop (7) to whose comparison circuit (43) an input pulse train (i) is applied and which is controlled by a clock pulse train (CPW). The phase comparison circuit generates intermediate pulse trains which comprise different parts of the input pulse trains and which are connected to filter circuits (53-58) which generate output pulse trains (i+, i-) which are proportional to the pulse density of the input pulse train (i). These input pulses are applied to a differential amplifier at whose output a voltage signal appears which is equal to the logarithm of the ratio of the output pulses and is therefore independent of the pulse density of the input pulse trains. A clock recovery circuit of this type can be used for 34 Mbit/s, PCM transmission systems according to CCITT Recommendations. <IMAGE>