| 摘要 |
PURPOSE:To prevent interference to other circuits, by detecting a malfunction of a phase locked loop of a clock generating circuit due to a strength of electric field and controlling the operation of the clock generating circuit and a signal conversion circuit. CONSTITUTION:A detection circuit 6 detecting the presence/absence of a synchronizing signal of the standard system consists of a retriggerable monostable multivibrator circuit having a pulse width being one horizontal period of the standard system or over, and when the synchronizing signal of the standard system is applied to the circuit 6, the output terminal goes to a high level at all time, and when not, the output terminal goes to a low level at all times. This detected output signal is applied to NAND gates 23 and 24 of a control circuit 11 so that a clock signal from a clock signal generating circuit 12 is not applied to a signal conversion circuit 4, allowing to prevent signal conversion when the synchronizing signal of the standard system is not applied to a PLL9. |
