| 摘要 |
PURPOSE:To realize the variable delay time inexpensively, by using plural stages of sample hold circuits without using expensive elements such as storage elements. CONSTITUTION:Plural sample holding circuits 1, 2...3 are connected in series, an input signal is applied to an input terminal 4 at the 1st stage, an output signal at an output terminal 5 of the final stage is applied to an LPF6 to obtain an output from an output terminal 7. A sampling pulse is generated from a sampling pulse generating circuit 8 and the phase of the pulse at the preceding stage is sequentially shifted at phase shifters 9, 10... and applied to the sample hold circuits 1, 2...3. The variable delay time is realized by changing the phase shift of the sampling pulse in phase-shifting the sampling pulse. |
