| 摘要 |
PURPOSE:To attain high speed switching operation by compensating the delay in the switching based on the reduction of the operating frequency due to the delay time in a multi-stage gate circuit by a holding function of a selector selecting optional one input among plural inputs and providing a latch circuit to the output side. CONSTITUTION:The titled circuit consists of a synchronizing flip-flop 10 arrang ing the location of the head of information (sound information, data, picture information or the like) subjected to time division multiplex on plural input HW 101-104, a selector 20 selecting an optional input among plural inputs HW 101-104 and giving an output, a gate circuit 30 holding the output of the selector 20 at the edge of the synchronizing clock pulse (CLK) for one clock period and a latch circuit 60 taking the synchronizing timing of the output HW 105. Thus, the number of passing gates in the channel switching circuit network between the input HW and the output HW is decreased, and the circuit copes with the transmission of moving picture information calling for a high speed switching.
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