发明名称 DIGITAL MULTI-FREQUENCY RECEIVER
摘要 PURPOSE:To prevent malfunction due to noise, by outputting a multi-frequency signal when the rate of change in power of an input signal is a prescribed value or below or when the multi-frequency code is changed. CONSTITUTION:A majolity logic circuit 16 outputs an SP signal to a terminal 14 when either or a code change detection signal (h) or a power attenuation detection signal (m) is inputted at least to an effective signal (e) inputted from a code check circuit 11, and the circuit 16 inputs a hold signal (f) to a code output circuit 13. The circuit 13 outputs a multi-frequency code (g) to a terminal 15 and holds the same frequency code (g) while the signal (f) is received. When an impulsive noise is inputted from a terminal 0, the rate of change in power (k) is larger than the threshold value 1, and the signal (m) is not inputted to the circuit 16. Thus, even if two effective frequencies are eventually detected on the way, no SP signal is outputted from the terminal 14.
申请公布号 JPS58151188(A) 申请公布日期 1983.09.08
申请号 JP19820033338 申请日期 1982.03.03
申请人 FUJITSU KK 发明人 TANAKA YASUO;OGAWA YASUNORI;HATANO TAKASHI;SHIMOZONO RIYOUJI
分类号 H04L27/26;H04Q1/457 主分类号 H04L27/26
代理机构 代理人
主权项
地址