发明名称 DECODING CIRCUIT OF SPLIT PHASE SIGNAL
摘要 PURPOSE:To improve the error rate of a circuit, by inverting the first or the latter half of waveform of each bit of a received split phase signal and applying it to an LPF. CONSTITUTION:When a reception split phase signal (a) is applied from a terminal 6, a clock reproducing circuit 8 forms a reproduced clock signal (b) based on a signal obtained via the LPF7 and applied to an analog multiplication circuit 9 and a delay circuit 12. The circuit 8 outputs ''1'' at the latter half of each bit of the signal (a) and ''0'' at the first half. Thus, an output signal (b) of the circuit 9 is subjected to a waveform inverting, e.g., the first half waveform of the signal (a) and leaving the latter falf waveform as it is. That is, the waveform of the signal (a) is equivalent to the reception waveform when the data is transmitted as a binary data. Then, the S/N of an output (f) of the LPF 13 is improved. The output signal (f) of the LPF 13 is applied to an FF14 together with an output signal (g) of the circuit 12, and an output signal (h) of the FF14 corresponds to the original binary data.
申请公布号 JPS58148552(A) 申请公布日期 1983.09.03
申请号 JP19820032104 申请日期 1982.03.01
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 ADACHI FUMIYUKI;HATSUTORI TAKESHI
分类号 H03M5/04;H04L25/49 主分类号 H03M5/04
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