发明名称 CONTROL BUS SYSTEM
摘要 PURPOSE:To reduce the number of interface lines between devices, by dividing control data and answer data into plural blocks to transfer them. CONSTITUTION:When a request to send control data is generated, a CPU1 sets a transmission/reception switching line to the transmission mode. In order to send the 1st block of the control data, the CPU1 sends the 1st block data to a data line, sets a transfer word number line to the 1st block display and sends a transmission synchronous signal. In the same manner, the CPU1 sends the 2nd block data to the data line, sets up the transfer word number line to the 2nd block display and sends a transmission synchronous signal in order to send the 2nd block. Thus the CPU1 divides the control data consisting of 32 bits into two blocks each of which consisting of 16 bits to send them to speed path equipment.
申请公布号 JPS58146924(A) 申请公布日期 1983.09.01
申请号 JP19820029586 申请日期 1982.02.25
申请人 FUJITSU KK;NIPPON DENSHIN DENWA KOSHA;OKI DENKI KOGYO KK;NIPPON DENKI KK;HITACHI SEISAKUSHO KK 发明人 FUKUI TOSHIMASA;HISHINUMA CHIAKI;MURATA NAOMITSU;OKAYASU MASAHARU;SEO TOMIHIDE;IWAMOTO YOSHIHARU
分类号 H04Q3/545;G06F13/36;G06F13/42 主分类号 H04Q3/545
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