| 摘要 |
PURPOSE:To realize a high-speed array operation, by using an effect of a high- speed vector process carried out with a vector processor using a vector register and at the same time performing the vector processors in parallel to each other. CONSTITUTION:A scalar instruction train for execution of a scalar processing unit SP and a vector array instruction train containing a vector instruction for execution of a central vector processing unit VPC and array instructions for execution of M units of vector processing units PE1-PEM are divided into a scalar instruction train and a vector array instruction and stored in a primary storage device C51. An access is given to these instruction trains by a primary storage control unit C52. The unit C52 gives answers separately to the access request given from the units SP, VPC and PE1-PEm respectively. |
