| 摘要 |
PURPOSE:To increase a switching speed by connecting an enhancement type IGFET which is connected to a clock pulse source at its gate to an enhancement-depletion type inverter circuit in series. CONSTITUTION:The drain 13 of a depletion type IGFETQ5 is connected to a constant power source VDD, the gate 14 and source 15 are connected to the drain 16 of an IGFETQ6 of the same type, and the source 18 is connected to the drain 19 of an IGFETQ7 of the same type to obtain an output terminal. Further, a clock pulse phi1 is applied to the gate 17 of an IGFETQ6 and the gate 20 of the IGFETQ7 is used as an input terminal. Therefore, since the pulse phi1 normally has large amplitude, the resistance when the IGFETQ6 is turned on is so much less than the resistance of the IGFETQ5 that it can be disregarded, thereby obtaining nearly the same switching speed with a convetional speed. |
