| 摘要 |
PCT No. PCT/US80/00673 Sec. 371 Date Jun. 2, 1980 Sec. 102(e) Date Jun. 2, 1980 PCT Filed Jun. 2, 1980 PCT Pub. No. WO81/03568 PCT Pub. Date Dec. 10, 1981.A dynamic random access memory (10) receives a memory address of a row decoder (14) which charges a selected row line (18). When the row line (18) is charged an access transistor (24) in a memory cell (22) is rendered conductive to connect a storage capacitor (26) to a bit line (30). The bit lines (30, 38) are previously set at an equilibration voltage. The voltage on the bit line (30) is driven slightly above the equilibration voltage if a high voltage state had been stored in the capacitor (26) or the voltage on the bit line is driven slightly below the equilibration voltage if a low voltage state had been stored on the capacitor (26). A sense amplifier (44) is connected to the bit lines (30, 38) and upon receipt of a latch signal (L) drives the one of the bit lines (30, 38) having the lower voltage to a low voltage state. A pull-up circuit (60) drives the voltage on the remaining bit line of the pair to a high voltage state, restoring the memory storage capacitor (26) to its initial state. After the row line (18) is now discharged trapping the original data state in the storage capacitor (26), precharge transistors (50, 52) then connect together the bit lines (30, 38) through a latch node (46) to share charge between the bit lines (30, 38) and drive the bit lines (30, 38) to the equilibration voltage.
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