发明名称 |
Combined integrated injection logic and transistor-transistor logic microprocessor integrated circuit design |
摘要 |
A microprocessor integrated circuit design has improved partitioning between integrated injection logic (I2L) and transistor-transistor logic (T2L) in the integrated circuit. An information bus structure incorporating a bidirectional input and output buffer and a bidirectional input and output multiplexer minimizes the number of internal bus lines in the integrated circuit. An improved T2- I2L interface circuit and structure supplies a T2L input to a plurality of I2L input stages, each having a restricted cross-sectional area resistor element in the base of an I2L input transistor. A storage register in the integrated circuit has a multiplexer portion provided at each flip-flop circuit of the register. A high speed feed forward flip-flop circuit is employed in registers of the integrated circuit where speed is critical. An improved voltage regulator and current source combination in a programmable logic array (PLA) reduces PLA temperature sensitivity. A pair of I2L clocking pulse input transistors in a T2L master-slave circuit avoids capacitive coupling problems and allows the master-slave circuit to operate over a much wider temperature range. A cycle counter for the micro-processor integrated circuit implemented as an improved ripple down counter requires a minimum number of gates while avoiding significant delay in operation.
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申请公布号 |
US4396980(A) |
申请公布日期 |
1983.08.02 |
申请号 |
US19800167614 |
申请日期 |
1980.07.11 |
申请人 |
FAIRCHILD CAMERA & INSTRUMENT CORP. |
发明人 |
HINGARH, HEMRAJ K. |
分类号 |
G06F9/32;G06F9/30;G06F15/78;H01L27/02;H03K3/288;H03K3/289;H03K19/018;(IPC1-7):G06F3/00;G06F7/48 |
主分类号 |
G06F9/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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