| 摘要 |
PURPOSE:To keep a DC balance by means of the redundancy of ternary recording and to lower the recording frequency to improve the S/N, by having a special structure with the same number of digits secured between +1 and -1 for a code consisting of (m) digits. CONSTITUTION:The input binary signals (binary codes) al are transferred successively by a clock C1 and a shift register 1, and a parallel data a2 of the prescribed bit is delivered and latched to a latch 3 with a clock C2 which is divided by a counter 2 that is reset with a synchronizing signal s1. The output of the latch 3 is applied to upper and lower ROM4 and 5, respectively, and the outputs of ROM4 and 5 are applied in parallel to shift registers 6 and 7. The outputs of registers 6 and 7 are converted into voltage waveforms by logic voltage converters 8 and 9 and then converted into ternary codes by a subtractor (adder) circuit 10. The same number of digits are secured between +1 and -1 with 2 consecutive numbers of +1 and -1 for the constitution of a code. At the same time, the continuation of +1 or -1 is avoided at both sides of the code. In such a way, the S/N is improved. |
