| 摘要 |
<p>Latch-up in CMOS devices (11c) by conduction of parasitic bipolar transistors (29c, 30c) is prevented by providing a voltage drop between the power supply voltage (V min cc) of the CMOS device and a voltage drop between the well region and ground. By providing these voltage drops, the parasitic transistors are prevented from conducting, and the channel lengths decreased, thus increasing current handling ability and decreasing switching times as compared with prior art CMOS devices.</p> |
