发明名称 MEMORY CONTROL CIRCUIT
摘要 <p>PURPOSE:To initialize a memory circuit without imposing on a processor part, by allowing an address counter to count up automatically by a basic clock once detecting a reset instruction. CONSTITUTION:Once an initial reset instruction is inputted, a flip-flop 22 is set through a signal line 2 to an initial state and the address counter 27 counts up. In a memory circuit 28, information is written in an address corresponding to the output of the counter. At this time, an AND gate 35 outputs logic ''0'' and information on the logic ''0'' is written in the memory circuit 28. When the address counter 27 goes up to a prescribed number, the address counter 7 is reset and at the same time, a flip-flop 2 is also reset to hold a signal line 23 at a logical level ''0'' and a signal line 34 at a logical level ''1'', thereby allowing DMA transfer.</p>
申请公布号 JPS58121432(A) 申请公布日期 1983.07.19
申请号 JP19820003796 申请日期 1982.01.13
申请人 NIPPON DENKI KK 发明人 MIYADERA KAZUYUKI
分类号 G06F1/24;G06F3/153;G06F12/02;G06F13/28 主分类号 G06F1/24
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