| 摘要 |
PURPOSE:To improve resolution without increasing the number of circuit elements by switching a reference voltage by a control signal which has a duty cycle corresponding to an input digital signal. CONSTITUTION:A master clock CLK is frequency-divided by a frequency dividing circuit 3 to obtain frequecy-divided pulse signals of various frequencies, which are inputted to a switch signal generating circuit 4. The input digital signal Din, on the other hand, is inputted to the generating circuit 4 through an input buffer circuit 5 to generate a switch signal having the duty cycle corresponding to the signal Din, and the signal is applied to a voltage dividing circuit 1. According to the switch signal, the voltage dividing circuit 1 divides reference voltages V1 and V2 and a filter and impedance converting circuit 2 smooths the divided voltages to generate an analog output voltage Vout. Thus, resolution is improved without increasing the number of circuit elements. |
