发明名称 Memory addressing circuit for converting sequential input data to interleaved output data sequence using multiple memories
摘要 A system for converting sequentially received data words, in the form of successively received groups of data words, into an interleaved output data word sequence, with each group of received data words consisting of T successive series of R data words. The system comprises N memories, each having W words locations, where WxN>/=TxR and where the N memories form a single memory matrix which is employed to process every group of received data words. Writing logic is provided for writing successively received data words of a first group of data words into the N memories in a predetermined sequence. Reading logic is provided for reading from the memories every Rth data word of the first group of data words written into the to leave an available word location in each instance where a data word was read therefrom. The writing logic also includes logic for writing successively received data words of each subsequently received group of data words into successively occurring available word locations created by the reading therefrom of the data words of the immediately preceding group of data words.
申请公布号 US4393444(A) 申请公布日期 1983.07.12
申请号 US19800204694 申请日期 1980.11.06
申请人 RCA CORPORATION 发明人 WEINBERG, LEONARD
分类号 G01S7/28;G01S7/292;G06F7/78;(IPC1-7):G06F7/00;G01S7/44 主分类号 G01S7/28
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