| 摘要 |
PURPOSE:To contrive the improvement of withstand voltages, by setting the distance between the outer periphery of the field plate of a base electrode of a planar type high withstand semiconductor device and the inner periphery of a protection ring at 5-15mum approx. CONSTITUTION:On an N epitaxial layer 2 on an N<+> Si substrate 1, a P base 3, an N<+> emitter 4, a P protection ring 5, an N<+> channel stopper 6, and P<+> connection layers 13 and 14 are provided, then insulation layers 7 and 7' are selcetively provided, and electrodes 9-12 are added. The base electrode 9 has the field plate 15 extended from a collector base junction to a collector layer 2, while a floating electrode 11 of the protection ring 5 has the field plate 16 extended from the outer periphery of the ring 5 to the side of the channel stopper 6. Thereby, when the distance L between the outer periphery of the plate 15 and the inner periphery of the protection ring is kept at 5-15mum approx., the field concentration generated by the curvature of junction is reduced by the plates 15 and 16, and accordingly the breakdown voltage (withstand voltage) of a device can be heightened. |
