发明名称 DEVICE CONTROLLING SYSTEM
摘要 PURPOSE:To reduce the number of steps to monitor a device efficiently, by providing a register, where different status data are set in accordance with processing conditions of the device, and a timer which monitors the time when a bit of this register has a prescribed polarity. CONSTITUTION:Status data stored in status registers REG of channels #0-#n are read through a bus (b) by a processing device MPU. Different processing states of each of channels #0-#n are indicated by respective bits constituting the register REG. The status signal read by the device MPU is set to a monitor register REG2, and respective bits of the register REG2 are monitored by timers T1-Ti. Polarities of the register REG2 are monitored by timers Tl-Ti to discriminate whether data indicates the ready state or not; and if the device is not ready, the device is restarted, and an overflow signal is set to an allocation register REG3 when a prescribed value is counted.
申请公布号 JPS58114118(A) 申请公布日期 1983.07.07
申请号 JP19810214010 申请日期 1981.12.26
申请人 FUJITSU KK 发明人 II TOSHIAKI;YAMAMOTO NOBORU
分类号 G06F13/10;G06F13/12 主分类号 G06F13/10
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