发明名称 NONVOLATILE MEMORY
摘要 <p>PURPOSE:To generate the writing/reading potential by means of a complete CMOS process, by forming a potential changeover switch with an enhancement type transistor to which a substrate electrode is connected in a prescribed way. CONSTITUTION:When the potential of a node 24 is set at a high level, the output of an inverter 90 having the prescribed threshold voltage is set at a low level with the output of an inverter 34 set at a high level respectively. Thus a potential changeover switch is formed. Then an enhancement type transistor 221 to which a substrate electrode and writing high potential are connected and an enhancement type transistor 23 to which a substrate electrode and an output node 5 are connected with a current path cut off with adjustment of the bias voltage and with a connection secured to the reading voltage VCC are turned on and off respectively. The writing high potential VPP is generated at the node 5. The reading potential VCC is generated in the same way without using a depression type transistor. Thus the writing/reading potential is generated with on-chip and by switching through a complete CMOS process in which the photoetching processes are decreased with the saved power.</p>
申请公布号 JPS58114396(A) 申请公布日期 1983.07.07
申请号 JP19810213616 申请日期 1981.12.26
申请人 TOKYO SHIBAURA DENKI KK 发明人 TANAKA SUMIO;WATANABE SHIGEYOSHI
分类号 G11C17/00;G11C16/06;G11C16/12 主分类号 G11C17/00
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