| 摘要 |
PURPOSE:To detect the presence/absence of a failure of a dissidence circuit and to improve the reliability of the system, by performing different data processing for each processor periodically and forcedly, and checking the detected output from a dissidence detection circuit. CONSTITUTION:A synchronizing pulse from a synchronism control section STC is applied to processors CPU1, CPU2 to synchronize them. Buses BUS1, BUS2 are connected to the CPU1, CPU2, and a dissidence detection circuit UAD monitoring data always is provided between the buses BUS1, BUS2, and the circuit UAD detects the dissidence between data processing of the CPU1 and CPU2. The output of the circuit UAD is inputted to input circuits IC1, IC2 connected to the buses BUS1, BUS2. Different data processing is forcedly executed to the CPU1, CPU2 periodically, the dissidence detection output of the circuit UAD is checked to detect the presence/absence of a failure of the circuit UAD. |
