发明名称 LOGICAL INTEGRATED CIRCUIT
摘要 PURPOSE:To detect all single short-circuit faults between decoding lines, product term lines, and output lines in a programmable logical array by adding simple checking logic irrelevantly to a normal logical function. CONSTITUTION:In an AND array 2, AND signals of signals of decoding lines where AND devices (corresponding to mark ''.'' at 211) are present are generated on respective product term lines 21-27, and in an OR array 3, OR signals of signals of product term lines where OR devices (corresponding to mark ''X'' at 311) are prevent are generated on respective output lines 31-33. Thus, normal output signals f1-f3 and a checking observation output signal (g) are obtained. In a decoder, if a short-circuit fault functioning as AND occurs between the input line of an external input signal x1 and the output line of an inverter 11, the fault can not be detected by a syndrome test of normal outputs f1-f3, but is detected from variation of said output signal (g).
申请公布号 JPS58108829(A) 申请公布日期 1983.06.29
申请号 JP19810190331 申请日期 1981.11.27
申请人 NIPPON DENKI KK 发明人 YAMADA TERUHIKO
分类号 H03K19/177;G01R31/02 主分类号 H03K19/177
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