| 摘要 |
PURPOSE:To eliminate the need for a work register and to speed up the multiplication processing, by executing a multiplier 2<i> with one stage of a shift circuit, and executing a multiplier 2<j> through the use of a partial word pickup and addition function, in multiplying a nuneral to be multiplied by 2<i>+2<j> (0<=j<=i). CONSTITUTION:The content of a register R0 is multiplied by 2<i>, that is, shifted left by the amount CN of shift designated with a shift circuit SFT and stored in the register R0. A value multiplying by 2<j> for the first input value of the content of the register R0 at an operation circuit ALU is picked up and summed to the content of the register R0 and the result is outputted to the register R0. The function part (f) of the instruction is decoded, a bit-length dl is picked up from the abit location ds of the register R0 represented in (r) at the process of operation of the operand is picked up and summed ALU' with the content of the register R0. That is, the partial word in the high-order (L side) than the bit location of i-j is picked up and summed. |
