| 摘要 |
PURPOSE:To reduce correlative errors, by inputting outputs of sample holding circuits of one or two systems to plural latch type A/D converters connected in parallel and processing these outputs. CONSTITUTION:A high-band analog signal ea from a terminal 20 is inputted to a sample holding circuit 22 through a buffer 21 and becomes a sample voltage eSH in the circuit 22, and this voltage eSH is supplied to latch type A/D converters 24a-24d through an amplifier 23. Converters 24a-24d quantitize the voltage eSH by four-phase clock signals phi1-phi4, and the quantitized amplitude value is encoded by an encoder before the next clock signal is inputted, and code signals D1-D4 are held in a latch circuit in time division. Signals D1-D4 become a digital signal D corresponding to the signal ea by a parallel-serial signal converter 25. Since the circuit 22 and the amplifier 23 are formed in one phase, the same sample voltage is applied to converters 24a-24d, and analog signals of the same level are not converter to different codes. |
