| 摘要 |
A hardware-saving method for rapidly multiplying two binary-coded operands is specified in which the multiplier loaded into a register is sampled at two fixed bit positions in accordance with a modified method of the mutiplicand multiples, one sample being carried out at the least-significant bit position in the register which is offset by about half the multiplier word length compared with the least significant bit position. The multiplicand multiples stored in a register record are progressively added, in accordance with the sampled figure coding, to the content of a work register to form in each case a partial product which is written back into the work register with displacement by one bit position towards lower-significant bits. With the writing-in of the respective partial product, the multiplier in the register is shifted by one bit towards lower-significant bits. The process occurs until all multiplier figures have been detected at both bit positions. The method is sufficiently accurate in spite of the great distance between the sampled multiplier figures and, additionally, can be implemented approximately just as quickly but with less hardware as known methods.
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