| 摘要 |
PURPOSE:To form a multistage delay line and a tapped multistage delay line, by connecting an arbitrary number of delay lines consisting of a switched capacitor (SC) circuit and an integration circuit in cascade. CONSTITUTION:An SC circuit 30 consisting of a switch and a capacitor stores analog signals temporarily. Switches 32-35 consist of MOSFETs. An integration circuit 50 comprising an operational amplifier 51, a capacitor 52 and a switch 53 outputs a signal when a signal charge of a capacitor 31 is transferred to the capacitor 52. In applying a pulse phi1 to a terminal 41, the capacitor 31 is charged, and when the pulse phi1 is disappeared, the charge is stored. Since a pulse phi2 is set on or off to a terminal 57, the integration circuit 50 is reset and the potential at a terminal 56 is zeroed. In setting a pulse phi3 to a terminal 42, a signal charge in the capacitor 31 is transferred to the capacitor 52 and an output delayed than an input signal by one period appears at the terminal 56. Signals inputted at each period are outputted with delay by one period each. |
