| 摘要 |
PURPOSE:To eliminate errors at a joint between lower-order and upper-order bits, by forming a reference voltage of a converter for the lower-order bit based on the output of a converter for the upper-order bit and providing an offset corresponding to the upper-order bit for this reference voltage. CONSTITUTION:A 3-bit parallel A/D converter 1 converts an analog input signal Vin into 3-bit digital signals H2-H6. In this case, a 68V upper limit reference voltage is applied to the converter 1 from a reference power supply 2 and a 4V lower limit reference voltage from a reference power supply 3. The signals H2- H0 are applied to a D/A converter 4, where the signals are converted into an analog voltage V4 having a value equal to 8 times the signals except for H2- H0=(111) and the analog voltage is applied to a converter 5 as a lower limit reference voltage. The V4 is offset at a DC power supply by 2 LSB of the signals H2-H6, i.e. 16V to from an analog signal V6, which is applied to the converter 5 as a upper limit reference signal. |
