METHOD AND DEVICE FOR CARRYING OUT CONVERSION BETWEEN A CYCLIC AND A GENERAL CODE SEQUENCE BY THE USE OF A HYPOTHETICAL ZERO BIT SERIES

摘要

On carrying out conversion between a cyclic and a general code sequence, each consisting of a succession of normal code blocks and an additional or shorter code block, a zero bit series is hypothetically assumed before the additional code block. In an encoder for producing a cyclic code sequence, the zero bit series is hypothetically placed before the additional code block by cooperation of a timing control circuit and a divider. In a decoder, a counter for timing an additional cyclic code block starts counting while another counter is still counting to time a next preceding normal cyclic code block, whereby the zero bit series is assumed.