| 摘要 |
PURPOSE:To obtain the semiconductor device whose turn OFF time is shortened with the increase in an ON voltage being suppressed as much as possible, by shortening the carrier life time in the vicinity of a first P-N junction corresponding to a region within 1/4 the width of a third semiconductor layer from the center of the third semiconductor layer in comparison with that of the other region. CONSTITUTION:A GATT is prepared by using a silicon wafer having the resistivity of 30-45OMEGA-cm as a starting silicon wafer. In the Figure, a numeral 5 shows regions where the life time is shortened, (a) is a distance from the center of an nE layer 4, and (b) is 1/2 the width of the nE layer 4. Referring to the correlation of the turn OFF time tq and an ON voltage VT, C is the case of a/b=1/2, and D is the case of a/b=1/3, and the conspicous effect is shown. In this method, it is found that the shortening of the life time in the vicinity of the center largely contributes the shortening of the turn OFF time in comparison with that at the peripheral part of the nE layer 4, when the turn OFF time approaches the life time in the vicinity of the junction J2. |
