| 摘要 |
PURPOSE:To simplify a titled circuit, by using the same clock CLK for phase difference measurement and signal delay, in a phase adjusting circuit in which the amount of phase delay of data signal of wired lined between base stations is adjusted constant through the use of radio lines. CONSTITUTION:A data signal SIG passes through a signal delay section 3 in a phase adjusting circuit 1, transits on wired lines 4 between base stations and is transmitted to a receiver 6 from a transmitter 5. The phase difference between the reception data and the signal SIG via an input line 7 is measured at a phase difference measuring section 2. This measured value L enters the section 3 via a delay information line 13, passes through an inverter 20 and is inputted to a decoder 14. Through the output, an outut of a shift register 15 delayed for a prescribed number of stages is selected at a selector 21 including an AND gate 22 and an OR gate 23 and outputted to the lines 4. That is, the time delay summing a delay -L of the section 2 and a delay L of the lines 4 can be made constant. |
