| 摘要 |
PURPOSE:To improve a calculation speed of multiplication, to reduce a necessary storage capacity, and to simplify the constitution of a multiplying device, by executing the multiplication by addition of once and subtraction of once, irrespective of the number of digits of multiplication. CONSTITUTION:A numerical value i<2> (a square value of i) of the i-th storage unit is stored in advance in a storage device 17, and with respect to inputted values A, B, contents R(A), R(B) of addresses A, B of the device 17 are written in registers 19, 20 of an adding circuit 18, addition R(A)+R(B) is executed, and its result is written in a register 23 of a subtracter 21. By keeping pace with this operation, the address calculation A+B, and contents R(A+B) of the A-th + the B-th addresses of the device 17 are stored in a register 22 of the circuit 21. Subsequently, by the circuit 23, subtraction of R(A+B)-(R(A)+R(B)) is executed, and the result is stored in a register 24. Subsequently, the upper 2L+1 digits which have subtracted the lowest bit 25 from the contents of the register 24 are outputted as a result 26, and the calculation of multiplication is executed at a high speed. |
