| 摘要 |
A general purpose retiming circuit comprising a timing signal source for generating timing signals, a plurality of N registers arranged in a row in a given order with each register having an input terminal, an output terminal, and clock input terminal and responsive to timing signals supplied thereto to transfer the signal supplied to said input terminal means to said output terminal. There is provided a serial input terminal for supplying a serial input signal thereto. Also provided are N switches arranged in the given order and each having first and second input terminals and an output terminal which is connected to the input terminal of a corresponding register of said row of N registers, and with the first input terminal of a first of the N switches being connected to the serial input terminal and the first input terminal of each of the remainder of the N switches being connected to the output terminal of the register preceding the corresponding register in the row of registers. Further provided in logic for supplying an N bit input signal in parallel manner to the second input terminals of the N switches. The N switches are actuated under control of timing signals generated by the timing signal source to selectively connect the first or second input terminals thereof to the output terminal thereof. Still further provided are N parallel output terminals, serial output terminals and a logic circuit responsive to timing signals generated by the timing signal source to selectively connect the output terminals of the N registers to the N parallel output terminals, the second input terminals of the N switches to the N parallel output terminals, and the output terminal of a selected register in the row of N registers to the serial output terminal.
|
