发明名称
摘要 PURPOSE:To achieve a simple circuit constitution which can alterate the number of bits and high speed operation, by making ineffective the output to the logic circuit of n stage of the ring counter constituted with m sets of FF and by interrupting the power supply on and after the n + 1 th state.
申请公布号 JPS5826858(B2) 申请公布日期 1983.06.06
申请号 JP19760160297 申请日期 1976.12.29
申请人 FUJITSU LTD 发明人 TAKEDA HIROSHI;YOSHIDA MAKOTO;KUDO OSAMU
分类号 H03K23/54;H03K23/64 主分类号 H03K23/54
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